1. Technical Field
The present invention relates to an A/D converter that converts an analog signal to digital data, and more particularly, to a successive approximation A/D converter.
2. Background Art
Successive approximation A/D converters sequentially compare the magnitudes of an input analog voltage with voltages (hereinafter, comparison target voltages) corresponding to ½, ¼ (or ¾) of a power supply voltage VDD to specify a comparison target voltage that is closest to the input analog voltage and output digital data representing the comparison target voltage. Successive approximation A/D converters are classified into a resistance division-type A/D converter, a charge redistribution-type A/D converter, and an A/D converter using the two types depending on a configuration of a circuit that generates comparison target voltages. It is generally difficult with the resistance division-type A/D converter to realize a resolution of 8 bits or higher. When it is necessary to realize a resolution of 8 bits or higher, a charge redistribution-type A/D converter or an A/D converter using both the resistance division type and the charge redistribution type is often used. JP-A-7-336224 and JP-B-7-34541 are examples of related art documents regarding a charge redistribution-type successive approximation A/D converter.
FIG. 5 shows a configuration example of a charge redistribution-type successive approximation A/D converter.
A comparator 20 compares the magnitudes of an input analog voltage Vin with a comparison target voltage. A reference voltage generation circuit 40 generates a reference voltage Vref (VDD/2 is used in the example of FIG. 5) used in the comparison by dividing a potential difference between a high potential power supply (a power supply generating an operation voltage VDD of the successive approximation A/D converter) and a low potential power supply (the ground) and supplies the reference voltage Vref to the comparator 20. A control circuit 30 includes an n-bit successive approximation register (not shown) and sets “10 . . . 0” (n-bit data of which only the MSB (Most Significant Bit) is 1 and the other bits are 0) to the successive approximation register as an initial value. The control circuit 30 causes a local D/A converter circuit 10 to generate a comparison target voltage corresponding to the content stored in the successive approximation register and updates the content stored in the successive approximation register with “11 . . . 0” or “01 . . . 0” in accordance with an output signal from the comparator 20. When the bit value of the LSB (Least Significant Bit) of the successive approximation register is determined, the control circuit 30 outputs the content stored in the successive approximation register as digital data which is the result of conversion.
The local D/A converter circuit 10 of FIG. 5 has capacitive elements C0, C1, C2, Cn-2, Cn-1, and Cn which form a binary-weighted capacitor array. Where n=4 and a unit capacitance is C, the capacitances of the capacitive elements C0, C1, C2, C3, and C4 are C/8, C/8, C/4, C/2, and C, respectively. In the successive approximation A/D converter shown in FIG. 5, the control circuit 30 first causes switches SW0, SW1, SW2, SW3, and SW4 to be switched to an input terminal side (a terminal to which the input analog voltage Vin is input) to turn ON a switch 12. In this state, the reference voltage Vref is applied to a common connection terminal of the capacitive elements C0 to C4, and an electric charge corresponding to the potential difference between the input analog voltage Vin and the reference voltage Vref is accumulated in the capacitive elements C0 to C4 (see FIG. 6A). A total electric charge QT accumulated in the capacitive elements C0 to C4 in the state shown in FIG. 6A is expressed by Equation 1 below.
                                                                        Q                T                            =                                                {                                                            V                      in                                        -                                          V                      ref                                                        }                                ×                2                ⁢                C                                                                                        =                                                {                                                            V                      in                                        -                                          VDD                      /                      2                                                        }                                ×                2                ⁢                C                                                                        (        1        )            
In the state shown in FIG. 6A, when the switch 12 is turned OFF, the total electric charge QT accumulated in the capacitive elements C0 to C4 is maintained. That is, the local D/A converter circuit 10 functions as a sample/hold circuit that converts the input analog voltage Vin to a potential difference “Vin−Vref” (hereinafter referred to as an internal analog voltage) between the input analog voltage Vin and the reference voltage Vref and holds the potential difference. Moreover, the local D/A converter circuit 10 has a function of generating various comparison target voltages under the control of the control circuit 30. In the successive approximation A/D converter shown in FIG. 5, successive comparison with various comparison target voltages is performed by opening the switch 12 to sequentially convert the switches SW0 to SW4. Conversion of these switches SWO to SW4 is performed in accordance with the content stored in the successive approximation register. Specifically, where the LSB of the successive approximation register is the 0-th bit and the MSB is the n-th bit, the control circuit 30 causes a switch SWk to be switched to the high potential power supply side if the bit value of the k-th bit (k=0 to n) is 1 and converts the switch SWk to the low potential power supply side if the bit value of the same k-th bit is 0.
In this way, at the start time of the successive comparison operation, “10000” is stored in the successive approximation register. Therefore, the control circuit 30 causes the switch SW4 to be switched to the high potential power supply side and causes the switches SW0 to SW3 to be switched to the low potential power supply side. As a result, as shown in FIG. 6B, the capacitive element C4 is disposed between the high potential power supply and a signal line L1, and the capacitive elements C0 to C3 are disposed in parallel between the signal line L1 and the low potential power supply. In the state shown in FIG. 6B, a voltage VM input to a minus-side input terminal of the comparator 20 is expressed by Equation 2 below, considering the fact that the law of conservation of charge (−C×(VDD−VM)+CVM=−2C×(Vin−VDD/2)) is applied to the electric charge accumulated in the electrode connected to the signal line L1.
                                                                        V                M                            =                              VDD                -                                  V                  in                                                                                                        =                                                VDD                  /                  2                                -                                  (                                                            V                      in                                        -                                          VDD                      /                      2                                                        )                                                                                        (        2        )            
The comparator 20 compares the magnitudes of the voltage VM shown in Equation 2 and a voltage Vp input to the plus-side input terminal thereof and outputs a signal corresponding to the result of the comparison. As shown in FIG. 5, since Vp=Vref(=VDD/2), comparing the magnitudes of VP and VM is equivalent to comparing the magnitudes of Vin and VDD/2. If Vin≧VDD/2, then VM≦Vp and a High level signal (“1”) is supplied from the comparator 20 to the control circuit 30. This means that MSB is 1. On the other hand, if Vin<VDD/2, then VM>VP and a Low level signal (“0”) is supplied from the comparator 20 to the control circuit 30. This means that MSB is 0.
When the bit value of the MSB is determined in this way, the control circuit 30 determines the bit value of 2SB (Second Significant Bit) which is the next bit in the following manner. For example, if the MSB is determined to be “1,” the control circuit 30 updates the content stored in the successive approximation register with “11000” and causes the switches SW0 to SW4 to be switched in accordance with the content stored in the successive approximation register. Specifically, in addition to the switch SW4, the switch SW3 is switched to the high potential power supply side. As a result, as shown in FIG. 6C, the capacitive elements C4 and C3 are disposed in parallel between the high potential power supply and the signal line L1, and the capacitive elements C0 to C2 are disposed in parallel between the signal line L1 and the low potential power supply. As described above, considering the fact that the law of conservation of charge is applied to the electric charge accumulated in the electrode connected to the signal line L1, the voltage VM appearing on the signal line L1 is expressed by VM=VDD/2−{Vin−(¾)×VDD}. The comparator 20 compares the magnitudes of the voltage VM and the voltage VP=VDD/2, and the 2SB is determined in accordance with the magnitude relationship between them (in other words, the magnitude relationship between Vin and (¾)×VDD). If the MSB is determined to be “0,” the content stored in the successive approximation register is “01000.” Therefore, the switch SW4 is switched to the low potential power supply side, and the switch SW3 is switched to the high potential power supply side. As a result, as shown in FIG. 6D, the capacitive element C3 is disposed between the high potential power supply and the signal line L1, and the capacitive elements C4 and C0 to C2 are disposed in parallel between the signal line L1 and the low potential power supply. In the state shown in FIG. 6D, VM=VDD/2-{Vin−(¼)×VDD}. Similarly, thereafter, 3SB (Third Significant Bit), . . . , and LSB are sequentially determined.
In recent years, there is a need for using a switching power supply and a DC/DC converter as a power supply that supplies a reference voltage VDD and suppresses the output voltage thereof to be low. However, since the output voltage of this kind of power supply contains a ripple component, when the output voltage is low, there is a problem in that the A/D conversion accuracy decreases greatly due to the fluctuation thereof. The reasons for this are as follows. It will be assumed that the output voltage of the high potential power supply is changed from VDD to VDD+ΔV when comparing the magnitude of the input analog voltage Vin and the comparison target voltages. In this case, although a fluctuation component of the voltage input to the plus-side input terminal of the comparator 20 is ΔV/2 regardless of the comparison target voltage, a fluctuation component contained in the voltage input to the minus-side input terminal thereof is different for each comparison target voltage. For example, the fluctuation component is ΔV/2 when the comparison target voltage is VDD/2 (namely, when determining the bit value of the MSB), and the fluctuation component is ΔV/4 or ΔV×(¾) when the comparison target voltage is VDD/4 or VDD×(¾) (namely, when determining the bit value of the 2SB). Therefore, if the power supply voltage fluctuates when determining the bit value of the bits other than the MSB, the magnitude relationship between the comparison target voltage and the input analog voltage Vin is not determined correctly. Thus, the A/D conversion accuracy decreases.